How to solve setup & Hold violations in the design ?

Solve setup & Hold violations in the design : 

To solve setup violation

1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx].
3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations.
4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten. the clock to launch-flop](otherwise called as Useful-skews) .

To solve Hold Violations

1. Adding delay/buffer[as buffer offers lesser delay, we go for spl Delay cells whose functionality Y=A, but with more delay].
2. Making the launch flop clock reaching delayed.
3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip].